PCI EXPRESS 2.0

PCI Express 2.0, the specification for interconnect technologies was released in early January 2007 which is essentially a revised version of earlier PCI Express. After much debating over the speed issue by industries which had taken the main centre stage of concern, the speed was fixed at 5.00Gbps, twice the existing 2.5Gbps. The doubling of speed means twofold increase in 16- lane link bandwidth from earlier 8 GB/s to 16 GB/s.   The wider bandwidth will prove a blessing for the users even as new applications emerge. Indeed insufficient bandwidth had always been a bottleneck for high performance applications. But it is a paradox that in the past, when computing power of the processor and bandwidth was available, corresponding applications were not known. Quite akin to this is the optical fiber whose immense bandwidth potential was discovered way back in 1960s, when World Wide Web and internet were not even heard of. It took nearly three decades to utilize the full bandwidth availability of the optical fiber.

Over the last decade, processor power and the bus speeds have been growing hand in hand and the growth has been mainly fuelled by the ever increasing consumer demand for graphics, audio and video streaming and server applications. The timing of new generation of PCI Express could not have been better when CPU Processors have entered a new era of QUAD core technologies with manifold increase in computing power and speeds. It is not surprising that the PCI special interest group has come with new revisions which could alleviate or remove the hurdles as seen in the earlier version of PCI Express and at the same time maintaining full backwards compatibility with hardware and software of PCI Express.

The doubling of speed and bandwidth in the new PCI Express 2.0 means tighter design conditions for designers and developers. It is no wonder that the new generation 3D gamer wants to have the finest textures and shades in his graphics and so the graphics card has to meet all the new stringent design specifications. At increased speeds, the main problem posed by the digital signals is jitter which if, is not within a specified limit can pose as a serious threat on signal integrity. The changes have been brought in the transmitter and receiver jitter specifications. A clear understanding of the differences can be made by looking at the following table explicitly describing the transmitter and receiver specifications at 2.5 Gb/s and 5.0Gb/s speeds.

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Spec Parameter  (PCIe1)  (PCIe2)   Units
Bit -rate    2.5    5.0 Gbps
Bit period   400 200 psec
Min Tx Eye width    TX-EYE 0.75 0.75 UI
Max. Tx Jitter   TX-JITTER 0.25(100) 0.25(50) UI(psec)
Dj Deterministic Jitter >1.5MHz TX-HF-Dj-OD Not specified 0.15(max) UI
Tx RMS Jitter TX-UF-RMS Not specified 3.0 Psec RMS
TTX-RISE-FALL Transmitter rise and fall time 0.125(min) 0.15(min) UI
VRX-EYE Receive eye voltage opening 175 120 mV
TRX-EYE Min Receive Eye width 0.4(160) 0.4 (80ps CCA,68psDCA) UI(pscec)
VRX-DIFF-PP-CC Differential RxVpeak-peak for common Refclk Rx architecture 0.175(min) 1.2 (max) 0.120(min)1.2(max) V
VRX-DIFF-PP-DC Differential RxVpeak-peak for  data clocked Rx architecture 0.175(min) 1.2 (max) 0.100(min)1.2(max) V
Receive Jitter Tolerance TRX-JIT-TOL 0.6 0.6 UI

 

 

Jitter values have been stringently specified in PCI Express 2.0 for all possible sources which have consequently put strict design control on circuits such as transmitter PLL (Phase locked loop),power supply noise, reference clock circuitry .Same is true on the receiver circuitry where minimum eye voltage aperture and jitter have been given tight budgeting

The signal is encoded by 8b/10b encoding which ensures isochronous transfers of signal with minimum latency. The PCI Express 2.0 comes with significant changes over its predecessor PCI Express at different levels of physical and protocol and software. The changes leverage on the modular structure of layered architecture of PCIExpress so that twofold increase in clock rates does not affect the upper layers. The Physical Interface for PCI Express Architecture (PIPE) defines the interface between PHY and DLL. Let us examine the following figure depicting the signal journey from user through interface and receiver.

 

 

The Physical layer PHY actually consists of two layers: electrical and logical. Electrical layer encompasses the realm of wires, silicon, PCB, interconnects and their geometries. In addition the new generation Physical media attachment or PMA consists of serializer, transmitter, receiver, deserializer and clock recovery circuits. The Logical layer is made up of  Physical coding sublayer blocks such as  8b/10b encode/decoding, elastic buffer, PRBS generator and checker, byte alignment circuits. Data link layer (DLL) and Transaction layer (TL) constitute the upper protocol layers and form a link to the uppermost layer that is user’s software or application layer. The DLL’s task is to provide link management and data integrity including error detection and correction. Transaction layer connects the lower protocol layer to upper layer by packeting the data and appending a header to it.

Let us look at other issues that have been addressed in the revised version of PCI Express. In the case of link width change due to hardware action or software retraining a mechanism of notification via an interrupt or associated status bit has been added. The extra signal to the software, apart from enabling dynamic link speed-width control, helps to take corrective action in case of failure of some link lanes, a feature which was not available in the previous PCI Express specification.

PCI Express 2.0 also comes with the new Access Control Services (ACS) to address the problems of communication faced between end to end points or multipoint device functions. Customers can selectively control access between endpoints or between functions of a multi-function device through well-defined interfaces. ACS is implemented as a set of capabilities and control register in the hardware and correspondingly ACS enabled software capability.          .

Functional changes in PCI Express2.0 also include addition of optional address space called Trusted Configuration Space to communicate and configure with PCI devices by issuing Trusted Configuration requests that give an assurance of design of computing platform with authorized software. Also added to PCI Express2.0 is  the new capability of setting completion time out value in the software .This helps in improved control in avoiding false triggering and greater situational appropriateness of Completion timeout handling.

Companies engaged in I/O virtualization technologies can look forward to the benefits brought about by the Alternative Routing-ID interpretation in PCI Express 2.0. The function capabilities of each device are increased while providing the same level of isolation and controls found in existing implementation. Another addition is Functional Level Reset which enables the software to stop and reset individual functions within endpoints and facilitates easy function reassignment from one virtual machine to another or one physical host to another.

Finally, many requirements in the full card and mini-card socket implementations are addressed. PCIe 2.0 cabling specification has included the use of a maximum 10 meters length of cable from the PCIe2.0 slot at a speed of 2.5Gbps, extending the use of remote expansion modules housing network adapter cards for high end servers.  Thermal design issues have been addressed especially for Wireless Wide Area Network mini add-on card designers .Further, PCI Express 2.0 has increased slot power budgeting to take care of the new generation of graphic cards consuming power greater than 255W

PCI Express 2.0 has also given heartening news to network/ storage solution providers. The SATA for storage is all slated to move to 6Gb/s from the present 3 Gb/s , making it well suited to the increased throughput per lane as the slot designs move to PCI express2.0, providing faster system  links to Ethernet controller and  Fiber channels.         .           The new specification for system bus has spawned a plethora of innovations from industry giants and technology providers. Chip giants Intel and AMD with its partner Nvidia   are set to roll out their accelerator and coprocessor chipsets supporting PCI Express2.0. Rambus Inc. is geared up with its Gen2. PHY integrated solutions to meet the technology needs of industry adapting to the new PCIe 2.0 standards. Concurrently, Test and Measurement solution providers like Agilent Technologies and National Instruments are clamoring to be ahead in the exciting race for this new technology. The challenge for them is to bring out the new generation of tools and equipment which could meet the testing needs of higher bandwidth and greater speed of PCI Express2.0 devices.

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